1. Field of the Invention
The present invention concerns a multilayer printed wiring board.
2. Description of the Prior Art
Electronic equipment, as represented by portable information terminals and communication terminals, are being made remarkably high in function and compactness in recent years. As a form of achieving high-density mounting of an IC chip used for such electronic equipment, onto a multilayer printed wiring board, the flip-chip method, with which the IC chip is surface-mounted directly onto the multilayer printed wiring board, is employed. As such a multilayer printed wiring board, one known multilayer printed wiring board includes a core substrate, a build-up layer formed on the core substrate, and mounting electrodes by which a IC chip is mounted via solder bumps on an upper surface of the build-up layer. The core substrate used in such a multilayer printed wiring board is prepared by molding an epoxy resin, BT (bismaleimide/triazine) resin, polyimide resin, polybutadiene resin, or phenol resin, etc. along with glass fibers or other reinforcing material. The thermal expansion coefficient of such a core substrate is approximately 12 to 20 ppm/° C. (30 to 200° C.) and is not less than approximately four times greater than the thermal expansion coefficient (approx. 3.5 ppm/° C.) of silicon of a IC chip. Thus with the above-described flip-chip method, there is the possibility that when temperature changes accompanying heat generation of the IC chip occur repeatedly, the solder bumps or the insulating layer of the semiconductor chip become broken due to the differences in the thermal expansion amounts and thermal contraction amounts of the semiconductor chip and the core substrate.
In order to resolve this problem, a multilayer printed wiring board, wherein a stress relaxing layer of low elastic modulus is disposed on the build-up layer, mounting electrodes are disposed on the upper surface of this stress relaxing layer, and a conductor pattern on the build-up layer is connected to the mounting electrodes by conductive posts, has been proposed (for example, see JP-A 58-28848 and JP-A 2001-36253).